NXP Semiconductors /LPC43xx /QEI /INTSTAT

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Interpret as INTSTAT

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INX_Int)INX_Int 0 (TIM_Int)TIM_Int 0 (VELC_Int)VELC_Int 0 (DIR_Int)DIR_Int 0 (ERR_Int)ERR_Int 0 (ENCLK_Int)ENCLK_Int 0 (POS0_Int)POS0_Int 0 (POS1_Int)POS1_Int 0 (POS2_Int)POS2_Int 0 (REV_Int)REV_Int 0 (POS0REV_Int)POS0REV_Int 0 (POS1REV_Int)POS1REV_Int 0 (POS2REV_Int)POS2REV_Int 0 (REV1_Int)REV1_Int 0 (REV2_Int)REV2_Int 0 (MAXPOS_Int)MAXPOS_Int 0RESERVED

Description

Interrupt status register

Fields

INX_Int

Indicates that an index pulse was detected.

TIM_Int

Indicates that a velocity timer overflow occurred

VELC_Int

Indicates that captured velocity is less than compare velocity.

DIR_Int

Indicates that a change of direction was detected.

ERR_Int

Indicates that an encoder phase error was detected.

ENCLK_Int

Indicates that and encoder clock pulse was detected.

POS0_Int

Indicates that the position 0 compare value is equal to the current position.

POS1_Int

Indicates that the position 1compare value is equal to the current position.

POS2_Int

Indicates that the position 2 compare value is equal to the current position.

REV_Int

Indicates that the index compare value is equal to the current index count.

POS0REV_Int

Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV_Int is set.

POS1REV_Int

Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV_Int is set.

POS2REV_Int

Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV_Int is set.

REV1_Int

Indicates that the index 1 compare value is equal to the current index count.

REV2_Int

Indicates that the index 2 compare value is equal to the current index count.

MAXPOS_Int

Indicates that the current position count goes through the MAXPOS value to zero in forward direction, or through zero to MAXPOS in backward direction.

RESERVED

Reserved

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